1. Field of the Invention
The present invention relates to a semiconductor device (including a semiconductor memory device) incorporating therein a memory cell array that has a plurality of static memory cells disposed in a row and column array, and more particularly to a semiconductor device in which a unit memory cell is constituted by a four transistor cell having transistors therein that serve as an access transistor (hereinafter, xe2x80x9ctransistorxe2x80x9d is abbreviated as simply xe2x80x9cTrxe2x80x9d) and also a load element, eliminating the need for a load resistor (hereinafter, this type of cell is referred to as xe2x80x9ca load less 4-Tr cellxe2x80x9d).
2. Description of Related Art
In a research and development of a semiconductor device having a static memory cell array therein, various load less 4-Tr cells having no load resistor and constituted by a unit cell consisting of two access Trs and two driver Trs have been proposed to reduce an area of a memory cell array or increase the number of memory cells contained in a unit area of semiconductor device. For instance, Japanese Patent Application Laid-open No. 13(2001)-167573 (hereinafter, referred to as a known example 1) discloses a static semiconductor memory device in which a unit memory cell consists of an access Tr and a driver Tr, both being an n channel field effect Tr (hereinafter, referred to as xe2x80x9cNMOSxe2x80x9d). Japanese Patent Application Laid-open No. 7(1995)-302847 (hereinafter, referred to as a known example 2), Japanese Patent Application Laid-open No. 12(2000)-124333 (hereinafter, referred to as a known example 3), Japanese Patent Application Laid-open No. 13(2001)-118938 and the like disclose an SRAM (Static Random Access Memory) memory cell consisting of an access Tr and a driver Tr, both being realized respectively by employing a p channel field effect Tr (hereinafter, referred to as xe2x80x9cPMOSxe2x80x9d) and an NMOS, or a static semiconductor memory device having therein the SRAM memory cell constructed as described above.
FIG. 12 is a circuit diagram illustrating the configurations of a memory cell Ml and a memory cell M3 of a semiconductor memory device disclosed in the known example 1. Referring to FIG. 12, the memory cell M1 comprises an NMOS 1072 connected between a bit line BL1 and a node N105, and having a gate connected to a word line WL1, an NMOS 1074 connected between a bit line /BL1 and a node N106, and having a gate connected to the word line WL1, an NMOS 1076 connected between the node N105 and a ground node, and having a gate connected to the node N106, and an NMOS 1078 connected between the node N106 and the ground node, and having a gate connected to the node N105. The NMOSes 1072, 1074 are referred to as an access Tr and the NMOSes 1076, 1078 are referred to as a driver Tr.
The memory cell M3 comprises an NMOS 1082 connected between the bit line BL1 and a node N107, and having a gate connected to a word line WL2, an NMOS 1084 connected between the bit line /BL1 and a node N108, and having a gate connected to the word line WL2, an NMOS 1086 connected between the node N107 and the ground node, and having a gate connected to the node N108, and an NMOS 1088 connected between the node N108 and the ground node, and having a gate connected to the node N107. The semiconductor memory device of the known example 1 operates as follows: the bit line BL1 and the bit line /BL1 are precharged during standby time to set the word lines WL1, WL2 at a voltage level a little bit higher than the ground level; and a current to retain data is stably supplied through the access Tr to a node included in the nodes N105 to N108 and maintaining a high level to allow a memory cell to reliably retain data. Note that when a memory cell is accessed, a word line to be selected is set to a high level and a word line unselected is set to the ground level.
FIG. 13 is a circuit diagram illustrating the configurations of an SRAM memory cell disclosed in the known example 2. Referring to FIG. 13, the SRAM memory cell comprises a pair of PMOSes 1101, 1102 as a selection Tr and a pair of NMOSes 1103, 1104 as a driver Tr whose drains and gates are cross-connected. To the PMOSes 1101, 1102 is supplied a power supply 1110 via bus Trs 1111, 1112 and bit lines 1107, 1108 that specify a Y address (column address). During standby time, a word line 1109 provided for specifying an X address (row address) and connected to the gates of the PMOSes 1101, 1102 is made to maintain an intermediate voltage level. Thus, an electric power is supplied by the power supply 1110 to a memory cell via the bus Trs 1111, 1112 and the bit lines 1107, 1108, thereby allowing the memory cell to hold data therein. A data read operation is performed as follows. First, the voltage level of a word line connected to an unselected cell is pulled up to disconnect a memory cell from a bit line. Subsequently, the gates of the bus Trs 1111, 1112 are set to a high level to stop supplying a power to the bit lines 1107, 1108. Thereafter, the word line 1109 connected to a selected cell is set to xe2x80x9c0xe2x80x9d V to make the PMOSes 1101, 1102 placed into a complete turn-on state, thereby reading data from the selected cell. As described above, a selection Tr is realized by employing the PMOSes 1101, 1102 and a driver Tr is realized by employing the NMOSes 1103, 1104, and during standby time, the PMOSes 1101, 1102 are made to operate as a pull-up element, thereby permitting a circuit designer to omit a pull-up element and allowing a semiconductor manufacturer to reduce process steps for the manufacture of semiconductor device to a large extent.
Additionally, FIG. 14 is a circuit diagram illustrating the configuration of a load less 4-Tr CMOS SRAM cell as a unit memory cell included in a semiconductor memory device disclosed in the known example 3. Referring to FIG. 14, the SRAM cell comprises PMOSes 1216, 1217 and NMOSes 1218, 1219. The gate, source and drain of the PMOS 1216 are connected respectively to a word line 1230, a bit line 1231 and a node 1233, and the gate, source and drain of the PMOS 1217 are connected respectively to the word line 1230, a bit line 1232 and a node 1234, and the gate, source and drain of the NMOS 1218 are connected respectively to the node 1234, the GND and the node 1233, and the gate, source and drain of the NMOS 1219 are connected respectively to the node 1233, the GND and the node 1234. The memory cell operates such that the word line 1230 becomes a high level in a standby state and a low level when the content stored in a memory cell is read therefrom or written thereinto. Furthermore in the semiconductor memory device of the known example 3, a gate length of each of the PMOSes 1216, 1217 is made larger that that of each of the NMOSes 1218, 1219. This construction of gate length suppresses an unfavorable influence of a phenomenon observed when a voltage applied to a drain makes a potential between a source and a channel lowered to thereby lower a threshold voltage, which phenomenon is called DIBL (Drain Induced Barrier Lowering), and makes a change of off-current caused by a potential difference applied between a source and a drain as small as possible, resulting in reduction of a standby current flowing through a memory cell.
A unit memory cell consisting of a load less 4-Tr cell is critically required to have an operating allowance called xe2x80x9cstatic noise margin (hereinafter, referred to as xe2x80x9cSNMxe2x80x9d) within which a memory cell is able to retain data therein over a longer period of time and operate at a further lower voltage, in addition to general electrical performances of SRAM, i.e., high speed operation, low power consumption specifically in terms of current consumption during standby time. Then, referring to FIG. 15, the SNM will briefly be explained below. For example, in a-case where a unit memory cell is configured to have PMOSes 1301, 1302 as an access Tr shown in FIG. 15A and NMOSes 1303, 1304 as a driver Tr to thereby constitute a load less 4-Tr cell, assume that the cell is divided into two inverters 1310, 1320 as shown in FIG. 15B. In such a state, a word line 1350 is set to a low level, and a gate potential Vg1 of the NMOS 1303 and a gate potential Vg2 of the NMOS 1304 are made to vary in a situation where a specific voltage Vd is applied to bit lines 1330, 1340. Under the above-described electrical conditions, the potential Vp1 of a node P1 and the potential Vp2 of a node P2 are measured, and then plotted and superimposed on the other in a graph shown in FIG. 15C, in which the potentials Vg1, Vp2 are indicated on the axis of abscissas and the potentials Vg2, Vp1 are indicated on the axis of ordinates. In this case, a maximum square C just housed within the area surrounded by a graph A corresponding to the inverter 1310 and a graph B corresponding to the inverter 1320 can be determined and then the SNM of the unit memory cell can be calculated as a voltage corresponding to the length of a side of the square C.
Regarding the above-described load less 4-Tr cell, various techniques for improving a data retention characteristic and reducing a standby current as a consumption current during standby time have been proposed. For example, in the known example 1, the low level of a word line is made a little bit higher than the ground level to pass a larger leakage current through an access Tr in a situation where the potential of a bit line is set to a high level during standby time, thereby allowing a memory cell to reliably retain high level data therein even in a case where variation in electrical performance of access Tr is generated owing to the process variation in the manufacture of semiconductor memory device.
Furthermore, also in the known example 2, the access Tr is constituted by a PMOS and a potential of a word line is set to an intermediate level during standby time to reliably retain high level data in a memory cell.
Moreover, in the known example 3, the gate length of the access Tr (PMOSes 1216, 1217) is made larger than that of the driver Tr (NMOSes 1218, 1219) to suppress an unfavorable influence of DIBL phenomenon observed in an access Tr, thereby reducing a standby current flowing through a memory cell.
In a load less 4-Tr cell consisting of an access Tr and a driver Tr realized respectively by employing PMOS and NMOS, assume that an on-current and an off-current of the access Tr are represented respectively by Ionp and Ioffp, and an on-current and an off-current of the driver Tr are represented respectively by Ionn and Ioffn. In this case, in terms of retention ability of memory cell, the ratio Ioffp/Ioffn is preferably made larger to maintain the potential of a storage node at a high level and in terms of improvement in the SNM during a read operation, the ratio Ionp/Ionn is preferably made smaller to maintain the potential of a storage node at a low level. However, in general, both a relationship between Ionp and Ioffp and a relationship between Ionn and Ioffn are positive, and therefore, it has been believed that optimizing an on-current and an off-current of each of an access Tr and a driver Tr is difficult because the data retention characteristic of a storage node and the SNM are in a trade-off relationship.
In consideration of the above-described problems found in the conventional techniques, the present invention has been conceived and directed to a semiconductor device incorporating therein a memory cell array constructed by disposing a plurality of unit memory cells consisting of a load less 4-Tr cell in a row and column array and achieving improved SNM while maintaining the data retention characteristic of storage node, and further, having an ability to operate at a further lower voltage.
An object of the present invention is to provide a semiconductor device incorporating therein a memory cell array formed so as to improve the SNM while maintaining the data retention characteristic of storage node and having an ability to operate at a further lower voltage.
A semiconductor device comprises a memory cell array having a plurality of unit memory cells disposed in a row and column array. In this case, the unit memory cell, includes first and second field effect transistors of a first conduction type, third and fourth field effect transistors of a second conduction type, and first and second resistance elements. The unit memory cell is further constructed such that a source/drain path of the first field effect transistor is connected between a first power supply and a first node, a source/drain path of the second field effect transistor is connected between the first power supply and a second node, a gate electrode of the first field effect transistor is connected to the second node, a gate electrode of the second field effect transistor is connected to the first node, a series-connected structure constructed by connecting a source/drain path of the third field effect transistor and the first resistance element in series is connected between the first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of the fourth field effect transistor and the second resistance element in series is connected between the second node and a second bit line paired with the first bit line, and both gate electrodes of the third and fourth field effect transistors are connected to a word line, thereby constituting a four transistor cell without a need for a load resistor.